1. Field of the Invention
The present invention relates to digital logic circuits, and more particularly, to an improved logic circuit which can be programmably connected to any one of a plurality of alternative voltage supplies and maintain a substantially constant current in its output circuit.
2. Description of the Related Art
Digital systems operate by performing basic logic functions, such as NOT, AND, OR, etc. The circuits which implement these basic logic functions in a digital system are called logic circuits (or logic gates). Logic circuits are the basic building blocks in any digital system.
Logic circuits are usually constructed from transistors, resistors, and diodes. One or more logic circuits are often arranged in a "macro-cell" and stored in a macro-cell library. It is not uncommon for only the unconnected transistors, resistors, and diodes to be arranged in a macro-cell in order to allow flexibility in implementing various different logic functions. Many macro-cells are then collected together and arranged in a pattern on an Integrated Circuit (IC) chip. This pattern of macro-cells is called a "gate array." The macro-cells are then interconnected during manufacture of the chip to form a unit that performs whatever function is needed. These chips are combined with other equipment, such as power supplies, video monitors, keyboards, etc., to form the digital system.
In order for a logic circuit to function it must be connected to some type of voltage supply. Each of the different families of logic circuits that have evolved over the years, such as complementary-symmetry MOS (CMOS), transistor-transistor logic (TTL), and emitter-coupled logic (ECL), have their own voltage supply requirements. Traditionally, most of the logic circuits within one family have the same voltage supply requirements.
It is becoming common, however, for logic circuits within the same family to be custom designed to operate from other than the traditional voltage supply levels. One might refer to these emerging custom designed logic circuits as "sub-families" of different types of gate array macro-cells within the family. One reason for this recent trend is that, while a user may be satisfied with the characteristics of one family of logic circuits, in certain applications the user may desire to use that family with a lower voltage supply level in order to dissipate less power. The result of this trend is that a user who has by great expense installed a special voltage supply in a digital system for use with these custom designed logic circuits can no longer use standard logic circuits of the same family because they cannot operate from the special voltage supply level. Conversely, a user who has maintained the standard voltage supply level in a system for use with standard logic circuits cannot use the new sub-families of custom designed logic circuits which have emerged.
Thus, although any given number of users may all use logic circuits of the same family, there is no longer a guarantee that these users have identical voltage supplies installed in their systems. This has created a frustrating situation for IC chip manufacturers who, in order to sell their product, must now ask the user what voltage supply levels are available and then custom design logic circuits that will operate from that voltage level. This process has slowed production and decreased profits due to the extra time and cost involved in creating a confusing line of sub-families of different types of gate array macro-cells whose basic logic circuit design has been permanently altered in order for them to operate with special voltage supply levels.
FIG. 1 illustrates an example of a conventional logic circuit 8 which is currently being used with various different voltage supply levels. The logic circuit 8 is of the Emitter-Coupled Logic (ECL) family and includes a voltage-comparator circuit 12 (also called a current switch or difference amplifier) and an emitter follower output circuit 14, connected as shown. In order to understand the complications which arise in designing this logic circuit 8 to function with different voltage supply levels, it is necessary to give a detailed discussion of its operation.
The logic circuit 8 is basically a buffer gate, although only one digital input Vin is shown. During operation a digital input signal Vin is received at the base of NPN transistor 18. The digital input signal Vin, which is generated by other logic circuits present in a digital system, has a certain predetermined "dynamic signal range" (also called a "logic swing"). A common dynamic signal range for ECL logic is about -1.5 Volts for LOW logic level to about -0.9 Volts for HIGH logic level. The voltage-comparator circuit 12 compares the input signal Vin to a constant reference voltage signal Vref which is received at the base of NPN transistor 20. The reference voltage signal Vref is set at the midpoint of the dynamic signal range, or at about -1.2 Volts.
The voltage-comparator circuit 12 determines whether the digital input signal Vin is at a HIGH or LOW logic level by determining whether it is above or below the reference voltage signal Vref. The manner in which transistors 18 and 20 and resistors 22 and 24 make this determination is well known in the art and will be explained in greater detail below. The result of this determination is that if the digital input signal Vin is at a HIGH level, then a HIGH level signal is generated at node 23; if the digital input signal Vin is at a LOW level, then a LOW level signal is generated at node 23. The signal generated at node 23 is then delivered to the base of NPN transistor 34 in the emitter follower output circuit 14.
As is well known in the art, the output voltage of an emitter follower circuit follows its input (base) voltage quite closely. Thus, if a HIGH signal is received at the base of transistor 34, then a HIGH digital output signal Vout is produced at output node 37. If a LOW signal is received at the base of transistor 34, then a LOW digital output signal Vout is produced at output node 37. It is vital that the digital output signal Vout have substantially the same dynamic signal range as the digital input signal Vin. This is because the digital output signal Vout will often be delivered to other logic circuits within the digital system which will all utilize the same dynamic signal range.
In order for the logic circuit 8 to function, it must be connected to four voltage supplies. A voltage supply Vcc is connected at node 30, a voltage supply Vcc02 is connected at node 36, a voltage supply Vee is connected at node 32, and a voltage supply Vtt is connected at node 39. These voltage supplies are needed for transistors 18, 20, and 34 to function as described above. The voltage supplies Vcc and Vcc02, which are not at issue in the present discussion, are often connected to separate grounds; the grounds are separate so that the noise generated by the emitter follower output circuit 14 does not leak into the comparator-circuit 12.
The voltage supply Vtt is at the very heart of this discussion because it is the voltage supply with which many users of ECL logic have chosen to use alternative voltage supply levels. While many users wish to lower the voltage supply level Vtt to conserve power, often times the user desires Vtt to be connected to and utilize the same voltage supply as Vee. This is because it is less expensive for the user to have a single voltage supply for both Vee and Vtt in his or her digital system rather than two separate voltage supplies. Vee can be either -4.5 or -5.2 Volts depending upon the strength of voltage supply used; therefore, in this scenario, Vtt utilizes this same -4.5 or -5.2 Volts.
In a high density gate array environment, however, where many thousands of logic circuits are connected together in a single gate array (the gate arrays forming the digital system), power dissipation becomes crucial. If a logic circuit uses less power then it will operate at cooler temperatures. The power dissipated in the emitter follower output circuit 14 is equal to the current Ief (the `current Ief` as used herein is intended to refer to the average current Ief) which flows through the resistor 38 multiplied by the voltage Vtt. It follows that if the voltage Vtt is reduced, and the current Ief stays the same, then less power will be dissipated. Thus, many users are using the logic circuit 8 with a lower Vtt; some commonly used reduced voltage levels for Vtt are -2.0 and -3.5 Volts. Because Vee must remain at either -4.5 or -5.2 Volts in order for the comparator circuit 12 to function properly, these users have by great expense had to install a separate voltage supply in their digital system in order to supply the reduced Vtt.
As discussed above, when alternative voltage supplies are used the logic circuit must be custom designed. The logic circuit must be custom designed because reducing the voltage supply level will have the effect of changing various current levels within the logic circuit. This is because, using logic circuit 8 as an example, when Vtt is connected to different voltage supply levels, the current Ief which flows through resistor 38 in the emitter follower output circuit 14 also changes. This phenomenon can be illustrated by a simple application of Kirchhoff's Voltage Law to the emitter follower output circuit 14: Ief=(Vout-Vtt)/Ref. Note that the digital output signal Vout remains substantially within its proper dynamic signal range even though Vtt is changed. This is because Vout is the output voltage of the emitter follower output circuit 14 and, as already stated, the output voltage of an emitter follower circuit will follow its input (base) voltage very closely. Therefore, since Vout remains substantially constant, and Ref is constant, Ief must change if Vtt changes. If Vtt is changed from -5.2 Volts to -2.0 Volts in order to reduce power dissipation, Ief will also be reduced in order to satisfy Kirchhoff's Voltage Law (the equation above). Thus, power, which equals Vtt multiplied by Ief will be reduced, but the current Ief will no longer be at its proper level. Therefore, in order to reduce power dissipation by changing Vtt and still permit the emitter follower output circuit 14 to function properly, the logic circuit 8 must be custom designed to maintain the current Ief at a constant level as Vtt is changed. In other words, there can be no change in Ief when Vtt is changed.
One custom designs the logic circuit 8 to maintain the current Ief at a constant level by varying the resistance Ref of the resistor 38. Referring again to Kirchhoff's Voltage Law, Ief=(Vout-Vtt)/Ref, it is easily seen that Ief can be maintained at a constant level if Ref is adjusted to compensate for changes in Vtt. Therefore, if Vtt is changed, Ief can be maintained at a constant level by changing Ref.
There are other reasons, besides power conservation, that the current Ief should be held at a constant level as Vtt is changed. An increase in Ief, due to a decrease in Vtt (e.g., -2.0 to -5.2), will decrease the switching time of the logic circuit, i.e., the time it takes the digital output signal Vout to switch from HIGH to LOW and vice versa. If the logic circuit is operating at this increased speed it may not function properly with other logic circuits within the digital system which may be operating at a reduced speed. Conversely, a decrease in Ief, due to an increase in Vtt (e.g., -5.2 to -2.0), will increase the switching time of the logic circuit. If the logic circuit is operating at this slower speed it may not function properly with other logic circuits which may be operating at an increased speed.
While varying the value of Ref may seem like a simple task to undertake in order to compensate for changes in Vtt, one must understand that these logic circuits are implemented in silicon. Once the silicon is formed to give Ref a certain value, Ref can no longer be changed. The logic circuit will operate with the correct current Ief only with the single value of Vtt that Ref was designed for. For example, if Ref is chosen so that the logic circuit will generate the proper current Ief using a Vtt of -2.0 Volts, the logic circuit can never be changed so that it will generate the same level of current Ief with a Vtt of -3.5, -4.5, or -5.2 Volts.
As mentioned above, a particularly frustrating situation has developed for IC chip manufacturers. These manufacturers must design and manufacture different logic circuits that can operate with each of the alternative voltage supplies that are currently used. For example, a manufacturer of the logic circuit 8 must manufacture a variation of this circuit that will generate a proper value of current Ief with a Vtt of -2.0 Volts, a variation that will generate the same value of current Ief with a Vtt of -3.5 Volts, a variation that will generate the same value of current Ief with a Vtt of -4.5 Volts, and a variation that will generate the same value of current Ief with a Vtt of -5.2 Volts. As can be seen, it would be highly desirable if there existed a single logic circuit that could function properly with any given one of a plurality of alternative voltage supplies which each supply different voltage levels.
Hence, there has developed a compelling need, particularly in the gate array environment, for an improved logic circuit that will operate properly when it is connected to any one of a plurality of alternative voltage supplies which each supply different voltage levels. This improved logic circuit must maintain the proper current levels in its output circuit no matter which voltage supply level it is connected to. In addition, there is also a compelling need, particularly in the gate array environment, for this improved logic circuit to be designed in such a way that it can be easily programmed to connect to and operate with the chosen voltage supply level.